1. Field of the Invention
The present invention relates to a computation processing circuit which executes logic computation for digital data and a computation method thereof.
2. Description of the Related Art
In recent years, electronic devices having a configuration that includes a digital computation processing circuit which provides high-speed computation, such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), etc., and memory which stores data obtained by the computation processing circuit, have become standard. Improvement of the functions of these electronic devices involves a progressive increase in the amount of data to be handled by the computation processing circuit and the memory.
In the computation processing by the CPU or DSP, in general, steps for reading an operand from the memory and steps for writing an operand to the memory are sequentially performed. As a result, in such a computation processing circuit, memory access becomes bottlenecked in the computation processing.
In view of such a situation, the present applicant has developed a technique for configuring a logic computation processing circuit having both a function as a computation processing circuit and a function as memory using ferroelectric capacitors (see Patent documents 1 and 2, for example). Such a technique allows a computation step and a memory writing step to be executed at the same time, thereby improving computation processing performance.
Patent Document 1
Japanese Patent Application Laid Open No. 2004-355671
Patent Document 2
Japanese Patent Application Laid Open No. 2004-264896